Introduction and Overview
OS_Memory calls have been updated. The following lists the reason codes which are allocated :
| Reason | Meaning |
|---|---|
| 0 | General block operations. See PRM 5a-62 |
| 1-5 | Reserved for internal use. See PRM 5a-64 |
| 6 | Read size of physical memory arrangement table. See PRM 5a-65 and this document |
| 7 | Read physical memory arrangement table. See PRM 5a-66 and this document |
| 8 | Read memory amounts. See PRM 5a-68 and this document |
| 9 | Read controller presence and logical base address. See PRM 5a-69 and this document |
| 10 | Lock free pool. See this document |
| 11 | Map PCI memory. See this document |
| 12 | Recommend page. See this document |
| 13-23 | Reserved for future expansion |
| 24 | Check memory access. See this document |
| 25 | Read controller presence and physical base address. See this document |
SWI Calls
| R0 | = | 6 (reason code), all flag bits are currently reserved and must be 0 |
| R1 | = | Table size |
| R2 | = | Page size |
This SWI is now deprecated.
| R0 | = | 7 (reason code), all flag bits are currently reserved and must be 0 |
| R1 | = | Pointer to table to fill in |
This SWI is now deprecated and may not return reliable information for a given OS version.
| R0 | = | 8 + flags:
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This SWI is used to read the amount of various types of memory available within the machine. On modern versions of RISC OS, the amount of VRAM will be returned as 0, as VRAM is now reserved to the video driver, rather than the Kernel. The new type 5 for softload RAM indicates the amount of memory allocated from DRAM (and excluded from the value returned for type 1).
| R0 | = | 9 (reason code), all flag bits are currently reserved and must be 0 | |||||||||||||||||||||
| R1 | = | Controller ID:
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| R0 | = | Preserved |
| R1 | = | Controller logical address |
This SWI is used to read the base address of a controller in logical address space. Under modern versions of the OS the correct way to obtain access to a controller is to create a dynamic area with the controller address mapped in to it. The Kernel will not map parts of hardware memory in future versions. This SWI is thus less useful in modern OS versions. Its behaviour has been changed slightly to correct an oversight in the original design. The original definition stated that 0 could be returned for an absent controller, in addition to an error being reported for an invalid controller. The implementation now returns an error for all controllers which do not exist, and 0 will not be returned.
See PRM 5a-69 for the original definition.
| R0 | = | 10 + flags:
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This SWI was allocated in RISC OS 4 for locking the free pool in order to implement Wimp_ClaimFreeMemory. The Wimp_ClaimFreeMemory call should not be used and this call is no longer used.
| R0 | = | 11 + flags:
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| R1 - R3 | = | Dependent on flags | |||||||||
This SWI was allocated in RISC OS 4 for mapping PCI memory within the Phoebe hardware. PCI memory allocation should now be performed by clients through the PCI manager module. The PCI manager module will use physical memory areas to provide drivers with memory mappings. This call is no longer used.
| R0 | = | 12 + flags:
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| R1 | = | Size of contiguous region of physical memory required in bytes | |||||||||
| R2 | = | Log base 2 of required alignment of base of region within physical memory, between 12 (4K) and 30 (2G) | |||||||||
| R3 | = | Page number of first page which fulfils the requirements specified |
This SWI is used to recommend pages of physical RAM which are unallocated and may be used for a new dynamic area. It is expected that they will be used to create a dynamic area, or to extend an existing area. An error will be returned if no pages match the required criteria. Prior to Kernel 8.77, bit 8 was not supported. This SWI call is available from RISC OS 4 onward.
| R0 | = | 24 (reason code), all flag bits are currently reserved and must be 0 |
| R1 | = | Low address |
| R2 | = | High address |
| R1 | = | Access flags:
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This SWI is used to determine the accessibility of a range of memory. It is similar to the SWI OS_ValidateAddress call in that it uses the Dynamic Area details to determine the availability of memory areas. The region from 'low address' to 'high address'-1 will be considered.
The flags returned indicate the access which is available for the range. Because the range may span (multiple) page boundaries the access for the range may vary across its length. Consequently, the two extents of accessibility are returned. Bits are separated into pairs of 4 bits. The lower 4 bits indicate the lowest level of accessibility for the region specified. The upper 4 bits indicate the highest level of accessibility for the region specified. If the bit sets are identical then the accessibility of the region does not change.
| R0 | = | 25 (reason code), all flag bits are currently reserved and must be 0 | |||||||||||||||||||||||||||||||||
| R1 | = | Controller ID:
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| R0 | = | Preserved |
| R1 | = | Controller physical address |
This call checks for the presence of a given controller and returns its physical address. This allows hardware drivers to provide support for specific controllers which may exist at different physical locations on other hardware. This call is similar to OS_Memory 9.