Real Time Clock


Contents


Introduction

The Real Time Clock has previously been handled by the Kernel. With Kernel 8.64 and later the clock is managed by the RTC module. This communicates with the hardware driver through a vector (RTCV) whose default claimant is the RTCHW module. The RTCHW module provides implementations for the RiscPC, A7000-series, RiscStation, and A9.

The RTC module provides the Kernel SWI OS_ResyncTime and all the OS_Word 14 and 15 operations to control the clock. A new reason code has been added to OS_Word 15 for setting the clock's 5 byte time directly.

A separate section describes the RTCV vector.


Service calls


Service_RTCSynchronised
(Service &DD)

Real time clock has been synchronised
On entry
R1=&DD (reason code)
On exit
R1preserved
Use

This service is issued by the RTC module to inform clients that the software and hardware clocks have been synchronised. It may indicate that an indeterminate period of inactivity has taken place, such as after returning from a suspend state. Where possible, timed events should be synchronised and where necessary appropriate action taken to ensure that queued events take place.

This service should never be claimed.

Related SWIs
OS_ResyncTime

SWI calls


OS_Word 15, 5
(SWI &7)

Set real time clock to UTC time as a 5-byte value
On entry
R0=15 (reason code)
R1=

Pointer to time values:

OffsetContents
+05 (sub-reason code)
+15 bytes of time value as centiseconds since 1900 in UTC

On exit
None
Interrupts
Interrupts are undefined
Fast interrupts are enabled
Processor mode
Processor is in SVC mode
Re-entrancy
SWI is not re-entrant
Use

This call is used to set the Real Time Clock to a time value as a UTC time. It avoids the requirement to convert a UTC time to a locale-specific time string first.

This call was new to RISC OS 4.

Related APIs
None

OS_ResyncTime
(SWI &6C)

Synchronisation operations for RTC
On entry
R0=

Reason code:

ValueMeaning
0Synchronise with hardware clock
otherReserved
On exit
None
Interrupts
Interrupts are undefined
Fast interrupts are enabled
Processor mode
Processor is in SVC mode
Re-entrancy
SWI is not re-entrant
Use

This SWI is used to cause the software clock to be resynchronised with the hardware clock, where available. When changed, a service call Service_RTCSynchronised will be issued.

This call was new to RISC OS 4.

Related services
Service_RTCSynchronised

Document information

Maintainer(s):
History:
RevisionDateAuthorChanges
12006GerphInitial version
  • Released as RISC OS Select documentation.
230 Dec 2021GerphPRM-in-XML conversion
  • Created from original Select documentation.
Related:http://www.riscos.com/support/developers/riscos6/time/rtc.html
http://www.riscos.com/support/developers/riscos6/time/osword15.html
Disclaimer:

© Gerph, 2021.